This board was designed to allow the AVR to offload processor intensive tasks to the FPGA. The AVR and the FPGA are connected by 28 IO pins (PORTC[0-3], PORTD, PORTE, and PORTF). This will allow for high speed data transfer. It was originally designed for a project I am working on which requires a large artificial neural network. The neural net will be modeled in hardware on the FPGA.

What exactly is the Fusion? Take a look at it’s features!

• XMEGA128A1
• Spartan 3A XC3S200A 5C
• 32MHz clock
• Real-time clock
• 16MB SDRAM
• 8MB DataFlash
• 3-axis accelerometer
• 2 general purpose LED connected to the XMEGA
• 1 general purpose LED connected to the FPGA
• 2Mbit FPGA PROM
• DONE LED for FPGA
• 5v-3.3V bi-directional level shifters
• 8 analog inputs (with 5V or 3.3V selectable power)
• 6 3.3V digital inputs
• 16 5V digital IOs
• 8 3.3V digital IOs
• Reset buttons
• Program button for FPGA
• Powered from 5V

The problem with FPGAs is the programmers are too expensive for most people. To combat this the FPGA will come loaded with a versatile design. It will allow for PWM on any of the pins, input capture on some, a hardware neural net, USART, and more.

The chip missing in the pictures is the DataFlash. I was not able to locate any stock right now but Atmel is sending a sample for this prototype.

So far I have identified two errors. The DONE label on the silkscreen should be next to the left LED not the right one and pins 20 and 19 on the 5v-3.3v level-shifters are flipped. I will patch that up tomorrow.