<![CDATA[Blog - Post Feed]]> https://embeddedmicro.com/blog Tue, 10 Oct 2017 22:05:13 +0000 Zend_Feed http://blogs.law.harvard.edu/tech/rss <![CDATA[Introducing Wave Capture in the Mojo IDE B1.3.0]]> https://embeddedmicro.com/blog/introducing-wave-capture The Mojo IDE has been updated to version B1.3.0. This release brings a handful of new features and many bug fixes, but the most notable new feature is the Wave Capture tool.

There is a new component called reg_interface_debug. This component is nearly identical to it's _debugless counter part from the Register Interface Tutorial with two major differences. The first is that addresses 0xfffffff0 through 0xffffffff can no longer be used. This is because these are reserved for the new debug input. This input allows you to feed up to 32 bits into reg_interface_debug that can then be viewed using the Wave Capture tool built into the Mojo IDE.

Take a look at this quick demo of the output of the pn_gen (pseudo-random number generator) component being captured.

The number of bits and the number of samples to capture are configurable. Currently you are limited from 1-32 bits and the number of samples is only limited by the available RAM in the FPGA.

With your FPGA project setup, to capture data you simply need to click the connect button followed by the capture button. The connect button tells the IDE to connect to the FPGA and read in some configuration data such as the number of bits and samples to capture as well as the version of the reg_interface_debug module (the version is shown in the top right corner). Once connected, the capture button sends the trigger settings to the FPGA and then starts a capture.

On the left, you can see four little icons. These are to set the conditions upon which a capture should start. You can select (from left to right) rising edges, falling edges, high-level, or low-level. You can toggle these on and off for any signal by simply clicking them. If you have multiple triggers in a signal selected then any of those will be interpreted as a start condition. However, if you have triggers set on multiple signals, all of them must be fulfilled to start a capture.

For example, if Bit 0 has rising and falling edges enabled, then either edge will trigger a capture. If you then enable high-level on Bit 1, a rising or falling edge on Bit 0 will only start a capture if Bit 1 is high when the edge occurs.

It's important to note that depending on what signals are being captured, it is possible to setup conditions that will never trigger. In that case you can simply cancel the capture (by clicking the capture icon again) and change your trigger conditions.

If you don't set any trigger conditions, it will start the capture as soon as possible.

To get started, check out the new Lucid example project, Wave Capture. This project shows how to hook up and use the new component.

This is the very first version of this tool so don't worry, we have many more features planned!

This version of the IDE adds a feedback form accessible from the Help menu (Help->Send Feedback...). We'd love to hear from you!

Sun, 08 Oct 2017 06:05:34 +0000
<![CDATA[Make Your Own CPU!]]> https://embeddedmicro.com/blog/make-your-own-cpu Have you ever wanted to make your own CPU? Now is your chance! We just published our latest tutorial, the Basic CPU Tutorial!

In this tutorial we walk you through the processes of creating a basic CPU that is under 100 lines long! You then get to write some assembly code that runs on the CPU. At the end of the tutorial, you will have all the tools you need to make your own modifications and programs.

It's pretty awesome to be able to write code for your own custom processor! What are you waiting for? Get started!

Tue, 10 Oct 2017 06:00:46 +0000
<![CDATA[August Shield Sale!]]> https://embeddedmicro.com/blog/august-shield-sale Well it's August and the end of Summer is in sight. But don't worry, we have your back! For the entire month of August, we are having some killer sales on our shields! Add some extra memory to your projects with the SDRAM Shield for only $24.99 (was $39.99), or start taking pictures with the Camera Shield for only $24.98 (was $34.98).

The sale also extends to our new shield, the IO Shield! The IO Shield is a great way to get your feet wet with FPGAs. It features a bunch of LEDs, switches, buttons, and even four seven-segment displays. Of course this shield wouldn't be complete without its own tutorial. That's why we have the IO Shield Tutorial to walk you through a ton of examples that should really help get a feel for how to make some FPGA projects of your own.

Sat, 07 Oct 2017 06:00:35 +0000
<![CDATA[Bay Area Maker Faire 2015]]> https://embeddedmicro.com/blog/bay-area-maker-faire-2015 The 2015 Bay Area Maker Faire is almost here (May 15th through 17th)! We have a booth again this year so if you're in the area make sure to come by and say hi! We have two free tickets for Friday and two more that can be used on Saturday or Sunday. Send us an email at support@embeddedmicro.com if you are interested.

This year we will be showing off (hopefully) a few new shields as well as some demos including our Mojo powered hexapod!

Tue, 10 Oct 2017 06:00:45 +0000
<![CDATA[Lucid and the Mojo IDE]]> https://embeddedmicro.com/blog/lucid-and-the-mojo-ide After 14 months of work, I finally get to share the new Mojo IDE with you! Before we get into all the cool new stuff, let me share some of the motivation behind everything.

Lucid, A New Hardware Description Language

Embedded Micro is all about making technology more accessible. We want FPGAs to be as easy to use as possible so anyone wanting to learn how to use one can without having outside training. After working with FPGAs for a while and talking to people who have been working with them far longer, the general consensus is that the tools are very poor. This is what we are trying to improve with the IDE. However, having a nice IDE is only half the battle. The other half is the language you are writing. Verilog and VHDL are both very cumbersome languages. They often require you to write the same or similar code in multiple places and don't allow for concise ways to instantiate basic primitives such as flip-flops. This is really because they weren't designed to be used with FPGAs but rather focused on simulations. Because of this, we knew we could do better so we created Lucid, a new hardware description language.

Lucid focuses on reducing the amount of code you need to write while promoting easily understandable designs. It is roughly based around Verilog, but shares some syntax from C/C++ (no more begin/end). We wanted your experience with FPGAs to be focused on learning about FPGAs rather than learning a complicated language. Lucid is similar enough to Verilog, and the concepts are the same as VHDL (or any HDL), so you shouldn't feel that you will be locked into writing Lucid. However, after writing Lucid for the past few months, I don't want to work in anything else.

Mojo IDE

As we said before, the other half of the battle is the IDE. The new version of the Mojo IDE, now supports Lucid with a ton of handy features. You can now update your Mojo's firmware, create a project based on various example project, add standard components, like I2C, SPI, and the AVR Interface, to your project, and get real time feedback on your code.

Our goal is to make the Mojo IDE a place where you enjoy working with FPGAs. We want you to miss its features when you have to use something else.

We are far from done with the Mojo IDE and Lucid. We are simply at a spot where we could no longer keep it to ourselves and had to share it with you! The IDE will auto-update so keep an eye out for the update prompt as we roll out even more features in the future!

Getting Started

Head over to the Mojo IDE page for the latest download links.

Once you have the Mojo IDE installed, check out the Lucid reference page.

Sun, 08 Oct 2017 06:05:33 +0000
<![CDATA[Firmware Update and Mojo V2]]> https://embeddedmicro.com/blog/firmware-update-and-mojo-v2 Mojo V2 is now Arduino Compatible!

We have added Arduino compatibility for the Mojo V2! We now have a slightly modified bootloader and support with our Arduino IDE plugin for version 1.6.x of their IDE. To get started, you will need to install the Arduino IDE and our plugin then flash the new bootloader.

We are very excited about this since it allows us to fully support the Mojo V2 and all our original Kickstarter backers with our upcoming projects. Keep in mind that some Mojo V2's were made with ATmega32U4 microcontrollers instead of the ATmega16U4 due to a stock shortage. If your Mojo V2 has an ATmega32U4, you should treat it like a Mojo V3 (they are electrically the same).

The only limitation of the ATmega16U4, is a lower maximum USB transfer speeds due to it having less RAM = smaller buffers.

New Firmware All Around

We have also made some modifications to both the AVR firmware and the Mojo Base Project for the Mojo V2 and V3. These modifications address the issue where sometimes some bytes would be dropped if you tried to send serial data as fast as possible. The new avr_interface module works exactly the same as before, so it should be a drop in replacement for your projects.

The old interface between the AVR and FPGA for sending serial data used a signal ( avr_rx_busy) for signaling that the buffer in the AVR was full and new data should not be sent. However, this was inadequate to prevent lost data. Each time a new byte is received, an interrupt is fired in the AVR that stores the data into a buffer to be later sent over USB. The problem occurs when two bytes are received before the interrupt handler has time to process the first one. In this case, the first byte will be lost. This happens when the AVR gets busy sending data over USB which has interrupts of its own preventing the bytes being processed in a timely manner.

The solution was to use the same avr_rx_busy signal, but instead of simply signaling when the buffer was full or not, to instead toggle each time a byte has been processed. This allows the FPGA to wait for the byte to actually be processed preventing any lost data.

With this new interface, you should enjoy reliable transfers with speeds around 48K bytes per second of one way transfer (tested as FPGA->PC) with the ADC disabled and 17K bytes per second with the ADC running constantly.

Sat, 07 Oct 2017 06:00:34 +0000